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? integrated circuits group LHF00L10 flash memory 32m (2mb 16) (model no.: LHF00L10) spec no.: el163051 issue date: march 11, 2004 p roduc t s pecific a tions

LHF00L10 ? handle this document carefully for it contains material pr otected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragrap h (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for ai rplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products covered herein to a sales represe ntative of the company. rev. 2.45
LHF00L10 1 rev. 2.45 contents pa ge 0.75mm pitch 48-ball csp pinout ............................. 3 pin descriptions.......................................................... 4 memory map .............................................................. 5 identifier codes and otp address for read operation ............................................. 6 otp block address map for otp program............... 7 bus operation............................................................. 8 command definitions ................................................ 9 functions of block lock and block lock-down...... 11 block locking state transitions upon command write........................................ 11 block locking state transitions upon wp# transition........................................ 12 status register definition......................................... 13 page 1 electrical specifications ........................................ 14 1.1 absolute maximum ratings........................... 14 1.2 operating conditions ..................................... 14 1.2.1 capacitance.............................................. 15 1.2.2 ac input/output test conditions............ 15 1.2.3 dc characteristics................................... 16 1.2.4 ac characteristics - read-only operations............................ 18 1.2.5 ac characteristics - write operations .................................... 20 1.2.6 reset operations...................................... 22 1.2.7 block erase, full chip erase, program and otp program performance. 23 2 related document information ............................. 24 3 package and packing specification........................ 25
LHF00L10 2 LHF00L10 32mbit (2mbit 16) flash memory ? 32-m density with 16-bit i/o interface ? read operation ? 90ns ? low power operation 2.7v read and write operations v ccq for input/output power supply isolation automatic power savings mode reduces i ccr in static mode ? enhanced code + data storage 5 s typical erase/program suspends ? otp (one time program) block 4-word factory-programmed area 4-word user-programmable area ? operating temperature -40 c to +85 c ? cmos process (p-type silicon substrate) ? flexible blocking architecture eight 4-kword parameter blocks one 32-kword block thirty-one 64-kword blocks top parameter location ? enhanced data protection features individual block lock and block lock-down with zero-latency all blocks are locked at power-up or device reset. absolute protection with v pp v pplk block erase, full chip erase, word program lockout during power transitions ? automated erase/program algorithms 3.0v low-power 10 s/word (typ.) programming 12.0v no glue logic 9 s/word (typ.) production programming and 0.8s erase (typ.) ? cross-compatible command support basic command set common flash interface (cfi) ? extended cycling capability minimum 100,000 block erase cycles ? 0.75mm pitch 48-ball csp ? etox tm* flash technology ? not designed or rated as radiation hardened the product is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.6v and v pp =1.65v-3.6v or 11.7v-12.3v. its low voltage operation capability greatly extends battery life for portable applications. the memory array block architecture utilizes enhanced data protectio n features, which provides maximum flexibility for safe nonvolatile code and data storage. special otp (one time program) block provides an area to store permanent code such as an unique number. * etox is a trademark of intel corporation. rev. 2.45
LHF00L10 3 a 8 wp# a 18 we# rst# nc dq 11 dq 12 dq 6 dq 13 dq 4 v cc 3 4 5 6 7 v pp a 19 a 6 a 9 dq 2 dq 5 dq 3 a 4 a 7 a 17 a 2 a 1 ce# dq 8 dq 0 dq 9 gnd oe# dq 10 a b c d e f a 5 a 3 a 0 dq 1 a 20 8 0.75mm pitch 48-ball csp pinout 7mm x 7mm top view a 13 a 14 a 10 a 12 dq 14 dq 15 v ccq gnd dq 7 1 2 a 11 a 15 a 16 figure 1. 0.75mm pitch 48-ball csp pinout rev. 2.45
LHF00L10 4 table 1. pin descriptions symbol type name and function a 20 -a 0 input address inputs: inputs for addresses. dq 15 -dq 0 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code, identifier code reads. data pins float to high-impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high (v ih ) deselects the device and reduces power consumption to standby levels. rst# input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rst# must be low during power-up/down. oe# input output enable: gates the device?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of ce# or we# (whichever goes high first). wp# input write protect: when wp# is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and not locked- down. when wp# is v ih , lock-down is disabled. v pp input/supply monitoring power supply voltage: v pp is not used for power supply pin. with v pp v pplk , block erase, full chip erase, program or otp program cannot be executed and should not be attempted. applying 12.0v0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin. applying 12.0v0.3v to v pp during erase/program can only be done for a maximum of 1,000 cycles on each block. v pp may be connected to 12.0v0.3v for a total of 80 hours maximum. use of this pin at 12.0v+0.3v beyond these limits may reduce block cycling capab ility or cause permanent damage. v cc supply device power supply (2.7v-3.6v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. v ccq supply input/output power supply (2.7v-3.6v): power supply for all input/output pins. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. rev. 2.45
LHF00L10 5 64-kword block 30 64-kword block 29 64-kword block 28 64-kword block 27 64-kword block 26 64-kword block 25 64-kword block 24 64-kword block 23 64-kword block 22 64-kword block 21 64-kword block 20 64-kword block 19 64-kword block 18 64-kword block 17 64-kword block 16 64-kword block 15 64-kword block 14 64-kword block 13 64-kword block 12 64-kword block 11 64-kword block 10 64-kword block 9 64-kword block 8 64-kword block 7 64-kword block 6 64-kword block 5 64-kword block 4 64-kword block 3 64-kword block 2 64-kword block 1 64-kword block 0 [a 20 - a 0 ] 000000 010000 01ffff 00ffff 020000 02ffff 030000 03ffff 040000 04ffff 050000 05ffff 060000 06ffff 070000 07ffff 080000 08ffff 090000 09ffff 0a0000 0affff 0b0000 0bffff 0c0000 0cffff 0d0000 0dffff 0e0000 0effff 0f0000 0fffff 100000 10ffff 110000 11ffff 120000 12ffff 130000 13ffff 140000 14ffff 150000 15ffff 170000 17ffff 180000 18ffff 190000 19ffff 1a0000 1affff 1b0000 1bffff 1c0000 1cffff 1d0000 1dffff 1e0000 1effff 160000 16ffff 4-kword block 39 4-kword block 38 4-kword block 37 4-kword block 36 4-kword block 35 4-kword block 34 4-kword block 33 4-kword block 32 32-kword block 31 1f0000 1f7fff 1f8000 1f8fff 1f9000 1f9fff 1fa000 1fafff 1fb000 1fbfff 1fc000 1fcfff 1fd000 1fdfff 1fe000 1fefff 1ff000 1fffff figure 2. memory map (top parameter) rev. 2.45
LHF00L10 6 notes: 1. block address = the beginning location of a block address. dq 15 -dq 2 are reserved for future implementation. 2. otp-lk=otp block lock configuration. 3. otp=otp block data. table 2. identifier codes and otp address for read operation code address [a 20 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 000000h 00b0h device code device code 000001h 00a0h block lock configuration code block is unlocked block address + 2 dq 0 = 0 1 block is locked dq 0 = 1 1 block is not locked-down dq 1 = 0 1 block is locked-down dq 1 = 1 1 otp otp lock 000080h otp-lk 2 otp 000081-000088h otp 3 rev. 2.45
LHF00L10 7 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000088h (dq 15 -dq 2) figure 3. otp block address map for otp program (the area outside 80h~88h cannot be used.) [ a 20 -a 0 ] rev. 2.45
LHF00L10 8 notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . refer to dc characteristics for v pplk and v pph1/2 voltages. 3. rst# at gnd0.2v ensures the lowest power consumption. 4. command writes involving block erase, full chip erase, program or otp program are reliably executed when v pp =v pph1/2 and v cc =2.7v-3.6v. 5. refer to table 4 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. refer to appendix of lhf00lxx series for more information about query code. table 3. bus operation (1, 2) mode notes rst# ce# oe# we# address v pp dq 15-0 read array 6 v ih v il v il v ih xxd out output disable v ih v il v ih v ih x x high z standby v ih v ih xxxxhigh z reset 3 v il xxxxxhigh z read identifier codes/otp 6 v ih v il v il v ih see table 2 x see table 2 read query 6,7 v ih v il v il v ih see appendix x see appendix read status register 6 v ih v il v il v ih xx d out write 4,5,6 v ih v il v ih v il x v pph1/2 d in rev. 2.45
LHF00L10 9 notes: 1. bus operations are defined in table 3. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. ia=identifier codes address (see table 2). qa=query codes address. refer to appendix of lhf00lxx series for details. ba=address within the block being erased, set/c leared block lock bit or set block lock-down bit. wa=address of memory location for the program command. oa=address of otp block to be read or programmed (see figure 3). 3. id=data read from identifier codes. (see table 2). qd=data read from query database. refer to appendix of lhf00lxx series for details. srd=data read from status register. see table 8 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. od=data within otp block. data is latched on the risi ng edge of we# or ce# (whichever goes high first) during command write cycles. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code and the data within otp block (see table 2). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rst# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. if the program operation and the erase operation are both suspended, the suspended program operation will be resumed first. 8. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. table 4. command definitions (10) command bus cycles req?d notes first bus cycle second bus cycle oper (1) addr (2) data oper (1) addr (2) data (3) read array 1 write x ffh read identifier codes/otp 2 4 write x 90h read ia or oa id or od read query 2 4 write x 98h read qa qd read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h full chip erase 2 5, 8 write x 30h write x d0h program 2 5,6 write wa 40h or 10h write wa wd block erase and program suspend 1 7, 8 write x b0h block erase and program resume 1 7, 8 write x d0h set block lock bit 2 write ba 60h write ba 01h clear block lock bit 2 9 write ba 60h write ba d0h set block lock-down bit 2 write ba 60h write ba 2fh otp program 2 8 write oa c0h write oa od rev. 2.45
LHF00L10 10 9. following the clear block lock bit command, block which is not locked-down is unlocked when wp# is v il . when wp# is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 2.45
LHF00L10 11 notes: 1. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, full chip erase and program operations. 3. at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (wp#=0) or [101] (wp#=1), regardless of the states before power-off or reset operation. 4. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock function which is different from those described above. notes: 1. "set lock" means set block lock bit command, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp# is not changed and fixed v il or v ih . table 5. functions of block lock (5) and block lock-down current state erase/program allowed (2) state wp# dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 001locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 101locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no table 6. block locking state transitions upon command write (4) current state result after lock command written (next state) state wp# dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change rev. 2.45
LHF00L10 12 notes: 1. "wp#=0 1" means that wp# is driven to v ih and "wp#=1 0" means that wp# is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 7. block locking state transitions upon wp# transition (4) previous state current state result after wp# transition (next state) state wp# dq 1 dq 0 wp#=0 1 (1) wp#=1 0 (1) - [000] 0 0 0 [100] - - [001] 0 0 1 [101] - [110] (2) [011] 0 1 1 [110] - other than [110] (2) [111] - - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] -[110]110 - [011] (3) - [111] 1 1 1 - [011] rev. 2.45
LHF00L10 13 table 8. status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pops vpps pss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = program and otp program status (pops) 1 = error in program or otp program 0 = successful program or otp program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the wsm (write state machine). check sr.7 to determine block erase, full chip erase, program or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, program, set/clear block lock bit, set block lock-down bit attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when v pp v pph1 , v pph2 or v pplk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/ otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are reserved for future use and should be masked out when polling the status register. rev. 2.45
LHF00L10 14 1 electrical specifications 1.1 absolute maximum ratings * operating temperature during read, erase and program ...-40 c to +85 c (1) storage temperature during under bias............................... -40 c to +85 c during non bias................................ -65 c to +125 c voltage on any pin (except v cc , v ccq and v pp ) ............................................... -0.5v to v ccq +0.5v (2) v cc and v ccq supply voltage .......... -0.2v to +3.9v (2) v pp supply voltage .................... -0.2v to +12.6v (2, 3, 4) output short circuit current ........................... 100ma (5) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc , v ccq and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on v pp may overshoot to +13.0v for periods <20ns. 4. v pp erase/program voltage is normally 2.7v-3.6v. applying 11.7v-12.3v to v pp during erase/program can be done for a maximum of 1,000 cycles on each block. v pp may be connected to 11.7v-12.3v for a total of 80 hours maximum. 5. output shorted for no more than one second. no more than one output shorted at a time. rev. 2.45 1.2 operating conditions notes: 1. see dc characteristics tables for voltage range-specific specification. 2. applying v pp =11.7v-12.3v during a erase or program can be done for a maximum of 1,000 cycles on each block. a permanent connection to v pp =11.7v-12.3v is not allowed and can cause damage to the device. parameter symbol min. typ. max. unit notes operating temperature t a -40 +25 +85 c v cc supply voltage v cc 2.7 3.0 3.6 v 1 i/o supply voltage v ccq 2.7 3.0 3.6 v 1 v pp voltage when used as a logic control v pph1 1.65 3.0 3.6 v 1 v pp supply voltage v pph2 11.7 12.0 12.3 v 1, 2 block erase cycling: v pp =v pph1 100,000 cycles block erase cycling: v pp =v pph2 , 80 hrs. 1,000 cycles maximum v pp hours at v pph2 80 hours
LHF00L10 15 test points v ccq /2 v ccq /2 input v ccq 0.0 output ac test inputs are driven at v ccq (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v ccq /2. input rise and fall times (10% to 90%) < 5ns. worst case speed conditions are when v cc =v cc (min). device under test r l =3.3k ? c l v ccq (min)/2 out cl includes jig capacitances. 1n914 figure 5. transient equivalent testing load circuit table 9. test configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 50 1.2.2 ac input/output test conditions 1.2.1 capacitance (1) (t a = + 25 c, f=1mhz) note: 1. sampled, not 100% tested. parameter symbol condition min. typ. max. unit input capacitance c in v in =0.0v 47pf output capacitance c out v out =0.0v 610pf figure 4. transient input/output reference waveform for v cc =2.7v-3.6v rev. 2.45
LHF00L10 16 rev. 2.45 1.2.3 dc characteristics v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions i li input load current 1 -1.0 +1.0 a v cc =v cc max., v ccq =v ccq max., v in /v out =v ccq or gnd i lo output leakage current 1 -1.0 +1.0 a i ccs v cc standby current 1,7 4 10 a v cc =v cc max., ce#=rst#= v ccq 0.2v, wp#=v ccq or gnd i ccas v cc automatic power savings current 1,4,7 4 10 a v cc =v cc max., ce#=gnd0.2v, wp#=v ccq or gnd i ccd v cc reset current 1,7 4 10 a rst#=gnd0.2v i ccr v cc read current 1,7 17 ma v cc =v cc max., ce#=v il , oe#=v ih , f=5mhz i ccw v cc program current 1,5,7 20 60 ma v pp =v pph1 1,5,7 10 20 ma v pp =v pph2 i cce v cc block erase, full chip erase current 1,5,7 10 30 ma v pp =v pph1 1,5,7 4 10 ma v pp =v pph2 i ccws i cces v cc program or block erase suspend current 1,2,7 10 200 a ce#=v ih i pps i ppr v pp standby or read current 1,6,7 2 5 a v pp v cc i ppw v pp program current 1,5,6,7 2 5 a v pp =v pph1 1,5,6,7 10 30 ma v pp =v pph2 i ppe v pp block erase, full chip erase current 1,5,6,7 2 5 a v pp =v pph1 1,5,6,7 5 15 ma v pp =v pph2 i ppws v pp program suspend current 1,6,7 2 5 a v pp =v pph1 1,6,7 10 200 a v pp =v pph2 i ppes v pp block erase suspend current 1,6,7 2 5 a v pp =v pph1 1,6,7 10 200 a v pp =v pph2
LHF00L10 17 notes: 1. all currents are in rms unless otherwise noted. typical values are the reference values at v cc =3.0v, v ccq =3.0v and t a =+25 c unless v cc is specified. 2. i ccws and i cces are specified with the device de-selected. if read or program is executed while in block erase suspend mode, the device?s current draw is the sum of i cces and i ccr or i ccw . if read is executed while in program suspend mode, the device?s current draw is the sum of i ccws and i ccr . 3. block erase, full chip erase, program and otp program are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.), and above v pph2 (max.). 4. the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t avqv ) provide new data when addresses are changed. 5. sampled, not 100% tested. 6. v pp is not used for power supply pin. with v pp v pplk , block erase, full chip erase, program and otp program cannot be executed and should not be attempted. applying 12.0v0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin and supplies the memory cell current for block erasing and programming. use similar power supply trace widths and layout considerations given to the v cc power bus. applying 12.0v0.3v to v pp during erase/program can only be done for a maximum of 1,000 cycles on each block. v pp may be connected to 12.0v0.3v for a total of 80 hours maximum. 7. for all pins other than those shown in test conditions, input level is v ccq or gnd. v il input low voltage 5 -0.4 0.4 v v ih input high voltage 5 2.4 v ccq + 0.4 v v ol output low voltage 5 0.2 v v cc =v cc min., v ccq =v ccq min., i ol =100 a v oh output high voltage 5 v ccq -0.2 v v cc =v cc min., v ccq =v ccq min., i oh =-100a v pplk v pp lockout during normal operations 3,5,6 0.4 v v pph1 v pp during block erase, full chip erase, program or otp program operations 6 1.65 3.0 3.6 v v pph2 v pp during block erase, full chip erase, program or otp program operations 6 11.7 12.0 12.3 v v lko v cc lockout voltage 1.5 v v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions dc characteristics (continued) rev. 2.45
LHF00L10 18 1.2.4 ac characteristics - read-only operations (1) notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. sampled, not 100% tested. 3. oe# may be delayed up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav read cycle time 90 ns t av q v address to output delay 90 ns t elqv ce# to output delay 3 90 ns t glqv oe# to output delay 3 20 ns t phqv rst# high to output delay 150 ns t ehqz , t ghqz ce# or oe# to output in high z, whichever occurs first 2 20 ns t elqx ce# to output in low z 2 0 ns t glqx oe# to output in low z 2 0 ns t oh output hold from first occurring address, ce# or oe# change 2 0 ns rev. 2.45
LHF00L10 19 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 20-0 dq 15-0 ce# oe# we# rst# high z t elqx valid output valid address t glqx t avav figure 6. ac waveform for read operations rev. 2.45
LHF00L10 20 1.2.5 ac characteristics - write operations (1), (2) notes: 1. the timing characteristics for reading the status register during block erase, full chip erase, program and otp program operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of ce# or we# (whichever goes low last) to the rising edge of ce# or we# (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of ce# or we# (whichever goes high first) to the falling edge of ce# or we# (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. v pp should be held at v pp =v pph1/2 until determination of block erase, full chip erase, program or otp program success (sr.1/3/4/5=0). 7. t whr0 (t ehr0 ) after the read query or read identifier codes/otp command=t avqv +100ns. 8. refer to table 4 for valid address and data for bl ock erase, full chip erase, program, otp program or lock bit configuration. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav write cycle time 90 ns t phwl (t phel ) rst# high recovery to we# ( ce# ) going low 3 150 ns t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 0 ns t wlwh (t eleh ) we# (ce#) pulse width 4 60 ns t dvwh (t dveh ) data setup to we# (ce#) going high 8 40 ns t av w h (t av e h ) address setup to we# (ce#) going high 8 50 ns t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns t whdx (t ehdx ) data hold from we# (ce#) high 0 ns t whax (t ehax ) address hold from we# (ce#) high 0 ns t whwl (t ehel ) we# (ce#) pulse width high 5 30 ns t shwh (t sheh ) wp# high setup to we# (ce#) going high 3 0 ns t vvwh (t vveh )v pp setup to we# (ce#) going high 3 200 ns t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp# high hold from valid srd 3, 6 0 ns t qvvl v pp hold from valid srd 3, 6 0 ns t whr0 (t ehr0 ) we# (ce#) high to sr.7 going "0" 3, 7 t avqv + 50 ns rev. 2.45
LHF00L10 21 t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t vvwh (t vveh ) t whqv1,2,3,4 (t ehqv1,2,3,4 ) t qvsl t qvvl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il (d/q) (w) (g) (e) (a) notes 5, 6 a 20-0 dq 15-0 (v) v pp v ih v pph1,2 v pplk v il v il (p) rst# ce# oe# we# v ih v il (s) wp# (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, oe# and ce# must be driven active, and we# de-asserted. "1" "0" (r) sr.7 t whr0 (t ehr0 ) notes 5, 6 figure 7. ac waveform for write operations rev. 2.45
LHF00L10 22 abort complete t plph t plph t 2vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst# rising timing rst# rst# v il v ih v il v ih v cc gnd v cc (min) rst# v il v ih sr.7="1" v oh v ol (d/q) dq 15-0 valid output high z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high z v oh v ol (d/q) dq 15-0 valid output high z t phqv t vhqv notes: 1. a reset time, t phqv , is required from the later of sr.7 going "1" or rst# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst# asserted while a block erase, full chip erase, program or otp program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. reset ac specifications (v cc =2.7v-3.6v, t a =-40 c to +85 c) symbol parameter notes min. max. unit t plph rst# low to reset during read (rst# should be low during power-up.) 1, 2, 3 100 ns t plrh rst# low to reset during erase or program 1, 3, 4 22 s t 2vph v cc 2.7v to rst# high 1, 3, 5 100 ns t vhqv v cc 2.7v to output delay 31ms figure 8. ac waveform for reset operations 1.2.6 reset operations rev. 2.45
LHF00L10 23 rev. 2.45 1.2.7 block erase, full chip erase, program and otp program performance (3) notes: 1. typical values measured at v cc =3.0v, v pp =3.0v or 12.0v, and t a =+25 c. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 4. a latency time is required from writing suspend command (we# or ce# going high) until sr.7 going "1". 5. if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes v pp =v pph1 (in system) v pp =v pph2 (in manufacturing) unit min. typ. (1) max. (2) min. typ. (1) max. (2) t wpb 4-kword parameter block program time 2 0.05 0.3 0.04 0.12 s t wmb1 32-kword block program time 2 0.34 2.4 0.31 1.0 s t wmb2 64-kword block program time 2 0.68 4.8 0.62 2.0 s t whqv1 / t ehqv1 word program time 2 10 200 9 185 s t whov1 / t ehov1 otp program time 2 36 400 27 185 s t whqv2 / t ehqv2 4-kword parameter block erase time 20.264 0.24s t whqv3 / t ehqv3 32-kword block erase time 20.515 0.55s t whqv4 / t ehqv4 64-kword block erase time 20.828 0.88s full chip erase time 2 40 350 33 350 s t whrh1 / t ehrh1 program suspend latency time to read 4510510 s t whrh2 / t ehrh2 block erase suspend latency time to read 4520520 s t eres latency time from block erase resume command to block erase suspend command 5500 500 s
LHF00L10 24 rev. 2.45 2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales offices. document no. document name fum03802 lhf00lxx series appendix

rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph v cc gnd v cc (min) rp# v il v ih (p) t phqv v ccw *1 gnd v ccwh1/2 (v) ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) wp# v il v ih (s) v oh v ol (d/q) data high z valid output t vr t f t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv t r or t f t r t r *1 to prevent the unwanted writes, system designers should consider the design, which applies v ccw (v pp ) to 0v during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. (v pph1/2 ) see the application note ap-007-sw-e for details.
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ?dc characteristics? describ ed in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit
s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5

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